Beyond Sequential Consistency

In 2011, C++ introduced a formally defined memory model, providing a foundation for portable, multi-threaded code with well-defined correctness guarantees. This was a major milestone, enabling expressive threading primitives and safe concurrency patterns while allowing low-level optimizations for performance. By default, C++ atomics enforce sequential consistency, which ensures intuitive, predictable behavior. However, these strong guarantees often exceed what’s necessary for correctness and come with a performance cost. This talk delves into weaker memory orderings, particularly acquire/release and relaxed semantics, using a ring buffer as a practical example of how they can be used. We’ll also examine how the C++ memory model maps to real hardware, focusing on x86’s native guarantees, and comparing against less coherent platforms like ARM. We'll explore how strategic use of weaker synchronization can unlock significant performance gains without sacrificing correctness.